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Interactive Design Tools: Integer-N RF PLLs : ADF4110/1/2/3 and ADF4106/7 Register Configuration Assistant
Instructions | Troubleshooting | Related Information


Instructions

There are four 24-bit registers in the ADF4110/1/2/3/06/07. In this calculator, each of the four registers is illustrated with field labels and user inputs corresponding to the bit fields in the real device. The width of the labels and elements is in proportion to the bit field widths: a checkbox is used for 1-bit fields, appropriately-sized pulldown menus for 2-16 choice fields, and numerical text boxes for fields longer than 4 bits.

Changing the state of a bit field recomputes the combined register value, expressed in hex, in a text box located to the right of each register. Conversely, changing the hex value in this box updates the individual bit fields that compose the register.

The counter fields can be automatically computed from user specifications for reference frequency, VCO frequency and channel spacing (top left). Internal frequency limits are checked which depend on the part and supply voltage (top center). When changing channel spacing, R-counter or prescaler values, the calculator attempts to preserve the VCO frequency, however, due to precision of the various counters, the frequency will tend to drift slightly.

RSET can be calculated from a maximum desired charge-pump current, ICP MAX, or the the maximum current can be found for a given RSET. These fields are independent of the other calculator fields.

Help for most fields is available by clicking on either the field title or the field form element. The help is shown in the yellow field at bottom and the field title should be similarly highlighted.


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Troubleshooting

For further troubleshooting information, please visit our Interactive Tools troubleshooting page.


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Related Information

ADF4110, ADF4111, ADF4112 and ADF4113 product pages


From Analog Dialogue: Phase-locked loops for high-frequency receivers and transmitters

Part 1: Introduction

Part 2: Phase Noise and Reference Spurs

Part 3: Architecture of PLLs


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